DESIGNING A RUNTIME SIMULATOR FOR QUEUE CORE PROCESSOR

ABSTRACT

In today’s era of modern architectures, high performance computing has received a lot of attention from diverse architectural levels. The performance crises in the computing arena have forced researchers to look for alternative architectures that will foster high performance whiles minimizing tradeoffs. The Queue Core processor is a novel 32-bit microprocessor that emerged as a result of the urgent desire for high performance microprocessor. The advent of the Queue Core processor has curb the performance crises due to its interesting features such as high Instruction Level Parallelism (ILP), dense program size, low power consumption, and elimination register concept. However, the demand in further improving the performance of the Queue Core processor has consequently triggered the growth in complexity. This has imposed a lot of constraints on the evaluation of Queue Processor with regards to timing, computations etc. Understanding of the internal dynamic mechanisms of the Queue Core Processor and their design space exploration therefore rely extensively on simulation tools which are traditionally software. In this research, we propose QSIM, a trace-driven and runtime simulator for the Queue Core processor. In QSIM, only a subset of the Queue Core Instruction Set Architecture has been implemented using the JAVA programming language. It is interesting to mention that this research work falls in the cross-road of two different domains: System Architecture and Software Engineering. The research will therefore be accomplished using methodical approach through the competent background knowledge of the Queue Core system architecture and application of Software Engineering principles. The advents of the QSIM amongst other benefits will principally offer an attractive opportunity to quickly evaluate the performance of the Queue Core Processor and serves as a tool to explore more Queue computation.

CHAPTER ONE (1)

1.0 INTRODUCTION

1.1 OVERVIEW OF QUEUE COMPUTING

Nowadays, the shift in Hardware and Software technology has compelled designers and users to look at micro-architecture that process instructions stream with high performance, low power consumption, and short program length. In striving for high performance, microarchitecture researchers have emphasized Instruction-Level Parallelism (ILP) processing, which has been established in superscalar architectures without major changes to Software. Since the program contains no explicit information about available ILP, it must be discovered by the Hardware, which must then also construct a plan of actions for exploiting parallelism. In short, computers have far achieved this goal at the expense of tremendous Hardware complexity – a complexity that has grown so large as to challenge the industry’s ability to deliver ever-higher performance. Queue Computing emerged as a new paradigm with an attractive alternative seeking to achieve the compulsive demand of high performance in micro-architectures. Queue Computing in simpler terms is the use of the Queues in processing/computation of data. Queue Computing uses the Queue Computation Model for its data processing. It has received much attention in recent years as an alternative architecture due to interesting features such as high parallelism capabilities, less instruction set, low complexity etc. Queue Computation Model (QCM) refers to the evaluation of expressions using a First-In First-Out (FIFO) Queue [9, 11], called Operand Queue. In this model, operands are inserted, or Enqueued, at the Tail of the Queue and removed, or Dequeued, from the Head of the Queue. Two references are needed to track the location of the Head and the Tail of the Queue. The Queue Head (QH), points to the head of the Queue. And Queue Tail (QT), points to the rear of the Queue. The concept of Enqueueing and Dequeueing extends to the operations allowed by the QCM. For example, binary and unary operations require two and one operands, respectively, to be Dequeued. After the operation is performed, the result is Enqueued back to the FIFO queue as illustrated in the diagram below (a+b and (a+b)/c are Enqueued after ADD and DIV operations respectively). We say that binary and unary operations Consume (Dequeued) and Produce (Enqueue) data. Some type of operations is Produce-only such as Load operation. Other types of operations are Consume-only such as Store operation. Queue Code is defined as the set of instructions executed by the QCM.

Department: Computer Science (M.Sc Thesis)

Format: MS Word

Chapters: 1 - 5, Preliminary Pages, Abstract, References, Appendix.

No. of Pages: 196

Price: 20,000 NGN

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